Citi & JPMorgan Evaluate Intel’s Potential Role in Manufacturing Google’s TPUs
In light of a recent report by The Information suggesting that Intel might produce Google’s proprietary tensor processing units (TPUs), analysts from Citi and JPMorgan have provided their insights on this development.
Intel’s foundry operations and its EMIB-T packaging technology have generated considerable speculation regarding the supply chain dynamics, particularly given Google’s partnership with Intel in the context of existing constraints at TSMC, positioning Intel as a potential alternative to the Taiwanese powerhouse.
Nevertheless, JPMorgan holds the view that TSMC will remain the primary manufacturer of these chips, with Intel tasked with the packaging component.
The buzz surrounding The Information’s report stemmed from the claim that Google had purportedly placed an order for three million TPU chips with Intel.
This assertion marked a departure from earlier reports that predominantly highlighted the collaboration for packaging technology.
In semiconductor parlance, packaging refers to the final assembly process where various chip components are integrated.
Intel’s EMIB-T presents a more economical alternative to TSMC’s sophisticated CoWoS technology, being particularly favored for lower-power custom AI applications.
Yet, JPMorgan asserts that the collaboration between Intel and Google is predominantly restricted to packaging rather than encompassing actual chip fabrication, contrary to the claims made in The Information’s report.
In its analysis, JPMorgan contends that the discussion appears to be “a tempest in a teapot,” lacking substantive new evidence.
It suggests that while tech giants like Google may contemplate Intel as a fallback for AI chip production, primarily due to TSMC’s constrained capacity, there is scant corroborative evidence for such assertions.
Specifically, JPMorgan challenges the report’s claim regarding the fabrication of three million TPUs at Intel, clarifying that these chips continue to be produced at TSMC, utilizing a 2-nanometer process for the compute die and 3-nanometer for the input-output die.
Moreover, Citi’s commentary resonates with similar skepticism. Their Taiwan semiconductor analyst, Laura Chen, has indicated that while the consensus among institutional investors perceives the report as focused on packaging, it could also encompass Intel’s foundry and design services alongside the EMIB-T technology.
JPMorgan underscores skepticism regarding the supposed “Intel deal.” It posits that The Information’s article seems to lack groundbreaking revelations, indicating that several prominent AI chip design companies, including Google and Nvidia, are in the mix.
Source link: Wccftech.com.
