IBM and Siemens Forge Alliance to Propel Advanced Nanosheet Transistor Architecture
In a strategic collaboration, IBM and Siemens have embarked on an initiative to enhance nanostack, a pioneering three-dimensional transistor architecture that boasts the extraordinary capacity to accommodate nearly 100 billion transistors within the confines of a fingernail-sized chip.
This alliance merges IBM’s profound expertise in semiconductor device research with Siemens’ advanced capabilities in electronic design automation (EDA), process simulation, lithography optimization, and manufacturing software.
Their mutual aim is to expedite development timelines and establish the manufacturing infrastructure vital for transitioning nanostack into commercial production.
Regarded by IBM as the first known 3D design utilizing nanosheet-based transistors, nanostack intricately arranges and offsets transistors in a vertical stack, thereby achieving unparalleled density compared to traditional planar architectures.
Presently operating at a 7-angstrom node, this innovative structure nearly doubles the transistor density per unit area relative to the nanosheet technology employed in IBM’s 2nm chips, unveiled in 2021.
This paradigm shift signifies a break from over six decades of semiconductor scaling confined to the X and Y dimensions.
By utilizing vertical stacking, nanostack opens the Z-axis, facilitating substantial density enhancements within a fixed chip footprint.
IBM likens this methodology to high-density urban development where constructing upwards on a limited parcel of land yields significantly increased usable space.
Furthermore, the ability to integrate diverse material combinations within each vertically stacked layer enables fine-tuning of performance and power consumption for individual transistors, without influencing adjacent components.
According to IBM, these innovations promise notable advancements in energy efficiency, overall performance, and SRAM scaling.
Huiming Bu, IBM’s vice president of silicon technology research and development, articulated: “Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D, representing a new paradigm for the semiconductor industry and paving the way for the logic scaling necessary to support AI and other emergent technologies over the next decade.”
Despite IBM’s demonstration of the architecture’s feasibility earlier this year, considerable further advancement is requisite prior to mass production.
The focus of this collaboration will be on the development of sophisticated virtual models of nanostack devices, which will allow the two companies to simulate performance, enhance designs, and identify potential manufacturing challenges before the physical production of chips begins.
Additionally, work is set to address the design, simulation, and lithography techniques essential for future iterations of nanostack beyond the initial 7 angstrom node.
Ankur Gupta, executive vice president of Siemens’ EDA IC portfolio, remarked: Scaling semiconductors into the angstrom era necessitates a tightly interwoven co-optimization among device physics, EDA design, manufacturing software, and production processes.
Given the extraordinary demands that physical AI places on silicon architecture, IBM’s 3D nanostack design stands as a critical advancement.
IBM first unveiled its breakthrough at the 7-angstrom level in June 2026, heralding the company’s entry into the domain of sub-nanometer chip fabrication.
Source link: Verdict.co.uk.
