The American technology powerhouse IBM has unveiled a groundbreaking strategy aimed at facilitating the fabrication of increasingly miniature semiconductor devices characterized by heightened transistor densities. This endeavor aspires to produce chips boasting structural widths of less than one nanometer.
IBM’s Innovative Method to Enhance Transistor Density
In recent years, Moore’s Law has encountered significant constraints, necessitating escalated efforts to achieve further reductions in the structural dimensions of contemporary chips.
IBM has now introduced its unique solution, aiming to escalate transistor density in forthcoming chips to attain theoretically calculated widths of a mere 0.1 nanometers.
The tech giant has crafted a manufacturing technique that currently enables the production of chips with structural widths as minimal as 0.7 nanometers, or 7 angstroms, aligned with existing standards for chip production nodes.
Transistor Architecture: Multi-tiered Configurations
IBM intends to implement advanced nanostacks, layering transistors vertically across multiple tiers. This design features several nanosheets—sheets of transistors—arranged in a staggered manner, thereby substantially amplifying transistor density while preserving the same footprint.
This innovative approach mitigates the necessity for further horizontal downsizing of structural widths.
The company has developed novel technologies allowing independent signaling and power delivery to the front and back of the staggered transistors across different tiers.
Through techniques such as single dielectric bonding, it is possible to optimize transistor performance independently at various levels.
Performance Boost: 50 Percent Enhancement Over 2nm
According to IBM, the newly conceived nanostack technology is applicable in a variety of contexts, including CPUs, GPUs, and memory products.
The anticipated results include a performance increase of up to 50 percent or an impressive efficiency enhancement of up to 70 percent compared to prevailing 2-nanometer chips.
It is crucial to note that IBM has yet to discover methods to compress the horizontal distances between transistors and other structures within a chip.
Essentially, the thrust is towards vertical expansion rather than horizontal reduction—a strategy previously adopted by TSMC, Intel, and other manufacturers.
However, unlike TSMC and others, IBM favors configuring multiple levels within its nanosheet architecture instead of merely stacking several wafer layers.
IBM has been leveraging nanosheets for some time to heighten transistor densities. However, the integration of this nanostack technology into commercial chips is projected to take several years.
The company estimates a timeline of approximately five years before reaching chips with a theoretical structure width of 0.7 nanometers.
As IBM has ceased chip manufacturing operations, third-party firms are empowered to license this technology, collaborating with IBM in the process.
Notable partnerships have already emerged, such as with the Japanese company Rapidus and Samsung.
Source link: Researchsnipers.com.
